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this post was submitted on 02 Sep 2024
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After you've done some languages, they all look the same. Yes, some have interesting features like the indent-based blocking of Python, and I'll have to look up if the new language has "else if", "elsif", "elif", or whatever, but als long as it is coming from the family of ALGOL-like languages, it does not matter much. You'll learn the basic functions needed to get around, and off you go.
Just a few weeks ago, I started learning Python. Yes, this indenting takes some time to get used to. My son does Python for about a year now - he started with it at university. Maybe ten days after I started learning, I invited him to have a look at my first Python program. I have no idea what he expected. A "Hello, World" with a few extra features, maybe? Definitely not the 2.5k lines app I had written in my spare time, with GUI, databases, harvesting data from a web site with caching, and creating PDF files with optimized layout for the data I processed. In the end, it was just another programming language.
I guess you've never seen some of the 10-page template errors C++ compilers will generate. I don't think anything prepares you for that.
I've seen way worse. Imagine a project that uses C preprocessor structures to make a C-compiler provide a kind-of C++. Macros that are pages long, and if you forget a single bracket anywhere, your ten pages look like a romance novel.
Or VHDL synthesis messages. You've got no real control over them, 99.9% of the warnings are completely irrelevant, but one line in a 50k lines output could hint at a problem - if you only found it.
So far, the output of C or C++ compilers (except for the above-mentioned project) has not been a problem or me, but I'm doing this for about 40 years now, so I've got a bit of experience.
I had to do a module programming in VHDL for my EE degree.
Every time I see it mentioned anywhere I have a compulsion to scream: FUCK VHDL AND ITS FUCKING ERRORS! NO YOUR ANALYSIS & SYNTHESIS IS UNSUCCESSFUL!
I did not pursue a career in electronics…
One of the key problems of learning VHDL at universities is that most teachers there are amazingly clueless about the language. Not only do you need a bit of a different mindset (you do not program, you define), but their knowledge of language and systems is stuck in the last century.
When I was a regular in a VHDL group on the site we don't mention here, we regularly had students who got taught techniques that are obsolete or at least deprecated since 1989.