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So why is 3 nm chip better?
(slrpnk.net)
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this post was submitted on 12 Sep 2023
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Until we have reliable and wide-temperature operating superconductors, electronics are limited by electrical resistance in the materials that conduct electricity. So the materials inside CPUs have resistance. With chemistry we've lowered it as much as we can, but for it to still be a semiconductor (the material that makes transistors and CPUs work) there are practical limits and we've hit those with humanity's knowledge today.
Take your hand palm flat and place it on the floor next to your foot. Put some weight on your hand and drag your hand quick from your toes to your heel. Your hand got a little warm from the friction, right? Now imagine doing that same hand dragging exercise from your bedroom all the way to your living room. HOT HOT HAND! Friction is the same thing that causes heat in CPUs. The friction is the electrons flowing rubbing against the resistance in the conductor.
So we've got heat limiting us, and the more distance we have, the more heat we have, the more limits on CPU speed we have.
So with present day CPUs, how can we make less heat? Use less distance in the CPU from place to place inside it.
This is where we come to your 3 nm (nanometers). This is the measurement of the width (of a part called the "gate") of one single transistor inside the CPU. Its 3 times smaller than say a 9 nm gate technology CPU. Our new CPU has 3 times less distance to travel which also means it needs less electricity to do the same work. Less electricity also means less heat because there fewer electrons rubbing against the conductor's resistance.
So less distance to travel, and fewer electrons needed to travel. Thats good stuff for making faster CPUs!
So now you ask, why are we stopping at 3nm? Why not 1nm right now? In short, we don't have the technology for it yet. CPUs are made with, believe it or not a photographic process! Light in the specific shape of the CPU circuit is shined on specially prepared silicon. Chemicals make part of that silicon conduct, and some part NOT conduct. This is semiconductor lithography. I could go down a whole separate line for this, but this isn't what you asked so I'll leave off right here.
please continue, sir. i like what i'm reading.
https://kbin.social/m/BestOf
That is where I found this thread.
Then thanks are in order!
Don't forget about capacitance. Longer distances == more capacitance to charge up on state transitions. This wastes power and puts a ceiling on how quickly you can switch.
I thought the big hold back for this size was the shenanigans around quantum tunneling messing up data in the CPU. How is that accounted for?
IIRC, anything less than 7-10nm is mostly marketing-speak anyway. Tunneling is a real limit at that scale, but chipmakers keep advertising smaller numbers as a performance-class figure rather than a physical size.
I was thinking the same thing
Really awesome answer, thanks!
I've never seen through of Friction in a Chip but this makes sense! Thank you that was a very very clear explanation!